As integrated circuit devices become more complex, interconnect and packaging technology becomes of greater importance to the design of such devices. This is because the interconnect and packaging technology used in a device can have a great affect on its functional capacity and utility.
Interconnection techniques are used to electrically connect multiple smaller functional units into more complex devices and to connect individual and multiple groups of smaller units to the package in which they will be contained. Interconnection methods are important because they affect the speed at which devices operate, the surface area required for the device, and the reliability of the device over an extended period of time. Packaging methods are also important because they affect the speed, cost and reliability of the device and provide the device with power and input signals. Due to the desire to increase the capacity of devices while maintaining a high level of reliability and minimizing cost, the interconnect and packaging technology used in manufacturing a particular device is an important consideration in the device's design.
A common method of producing a complex device from multiple individual devices is to use Multi-Chip Module (MCM) packaging technology. MCM technology combines two or more individual integrated circuit (IC) dice or chips into a single package which is capable of performing more complex functions than a single IC chip. The individual chips are mounted on a common substrate and connected to the substrate (and to each other by virtue of the interconnect network on or within the substrate) and to package contacts by one of several methods, for example, wire bonding or solder bump technology. Wire bonding involves connecting bonding pads or contacts on an IC chip to a lead frame or to pads or contacts on other chips with fine wires. Interconnections between contacts on different IC chips can also be carried out by soldering connecting wires between them or using metal interconnect lines.
While using fine wires or metal interconnect lines to interconnect IC chips to any desired degree is possible in theory, the number of interconnections required is often not practical because of constraints on the space available for routing interconnect wires or lines, the need to limit the number of interconnections in order to prevent short circuits, and because capacitive and inductive coupling between the wires or lines can degrade performance. Owing to these considerations, efforts have been made to optimize interconnect schemes and to develop other methods for interconnecting multiple IC chips into a larger and functionally more complex device.
As mentioned, individual chips can also be mounted on a common substrate by using solder bump or flip-chip technology. In this method, solder bumps are placed on the die and the chip is flipped over, placing the solder bumps in contact with conductive pads on the substrate. The solder is then reflowed, establishing a good electrical contact. The individual chips are again interconnected to each other using an interconnect network embedded on or within the substrate.
An example of a MCM technology which is suited for applications requiring a large number of interconnections between the individual chips and which uses such an interconnect network is Area Array technology. In this packaging method, connections are made from the interior of one chip to another through interconnect lines embedded on or within a multi-layer MCM substrate. The interconnect layers of the substrate are accessed through arrays of conductive pads which are designed to correspond to the positions of the metal bumps on chips used in flip-chip packaging methods. The metal bumps are soldered to the array pads to electrically connect the chips to each other.
The need for additional interconnect capacity beyond that obtainable using wire bonding or metal interconnect lines is especially critical when interconnecting arrays of logic cells or chips composed of multiple logic cell arrays into larger and more complex devices. Since logic cell arrays typically require a large number of connections in order for the smaller arrays to be combined into a higher capacity logic device, as the final array becomes larger, a barrier to further expansion is quickly reached. This is because of the need to avoid the inherent problems with wire bonding or metal interconnect lines mentioned above. The result is that the array is constrained to either being small, but limited in complexity, or complex, but larger and more expensive than may be desired for a given application.
A method of forming a large scale integrated circuit by stacking two or more layers of chips onto each other and interconnecting them via wire bonding is described in Japanese Patent Application Disclosure No. 1-28856, corresponding to Application No. 62-182307, entitled "Multilayered Integrated Circuit", filed Jul. 23, 1987 and naming Takeuchi as the inventor. While this disclosure describes a means of combining two or more IC chips to provide a larger circuit, the use of wire bonding to interconnect the chips makes the package liable to the space availability, short circuit and capacitive and inductive coupling problems noted above. Thus, the interconnect capacity of such a device is severely limited.
U.S. patent application Ser. No. 08/190,910, entitled "Extendible Circuit Architecture", which is assigned to the same Assignee as the present application and lists as inventor one of the inventors of this application, describes and claims a high gate capacity programmable module for which the semiconductor material cost increases linearly with gate capacity, and is hereby incorporated by reference to provide additional background information regarding the present application. The module is manufactured by taking a single device having a two dimensionally extendible architecture and utilizing it in a packaging method based on Area Array technology. The result is that multiple individual chips are interconnected into a single, larger device by means of a MCM packaging technique. Because each individual chip is two dimensionally extendible, the resulting larger capacity device is functionally equivalent to the smaller devices from which it is made. The final device has substantially the same architecture, but an increased gate capacity when compared to the smaller devices.
While both the two dimensionally extendible architecture described above and other MCM packaging methods permit the manufacture of more cost-effective high capacity devices, a problem relating to the interconnect network used in such devices still exists. This problem concerns the propagation delays introduced by routing signals to the periphery of a die or chip before interconnections are made to other elements. Such routing can vastly decrease the operating speed of a device since a signal may have to propagate along excessively long paths or through extraneous circuit elements prior to being received at its intended destination.
What is desired is a method of interconnecting multiple smaller logic cell arrays or chips into a more complex device using an interconnect method which reduces the average interconnect distance between any two smaller elements and overcomes the noted problems associated with wire bonding and other existing interconnect schemes.